A CPU with 50 billion transistors is built from a single repeated idea: a transistor is a switch. Everything else — math, memory, programs — emerges from switches connected in patterns.
A MOSFET transistor has three terminals: gate, source, drain. Apply voltage to the gate and current flows from source to drain — the switch is ON. Remove voltage and current stops — the switch is OFF. At 3nm process nodes, each transistor is 3 nanometers wide. An Intel Core i9-13900K has 25 billion transistors packed on a fingernail-sized die.
Connect two NMOS transistors in series: current only flows if BOTH gates are high — that's an AND gate. Connect two in parallel: current flows if EITHER gate is high — OR gate. Invert the output and you get NAND/NOR. Every logic gate is 2–6 transistors. Every digital computation is built from these.
Logic gates implement Boolean algebra. AND: A·B. OR: A+B. NOT: Ā. XOR: exclusive-or, true when exactly one input is true. Every arithmetic operation, every comparison, every data movement in a CPU is ultimately AND/OR/NOT operations on bits. The CPU doesn't understand numbers — it understands voltages that we interpret as 0s and 1s.
# Logic gates in Python — simulate transistor behavior
def NAND(a, b): return not (a and b) # 2 transistors
def NOT(a): return NAND(a, a) # 2 transistors
def AND(a, b): return NOT(NAND(a,b)) # 4 transistors
def OR(a, b): return NAND(NOT(a), NOT(b)) # 6 transistors
def XOR(a, b): return AND(OR(a,b), NAND(a,b)) # 10 transistors
# Half adder: 1-bit addition
def half_adder(a, b):
sum_bit = XOR(a, b) # sum
carry_bit = AND(a, b) # carry
return sum_bit, carry_bit
# Full adder: adds two bits plus carry-in
def full_adder(a, b, cin):
s1, c1 = half_adder(a, b)
s2, c2 = half_adder(s1, cin)
return s2, OR(c1, c2)
# 4-bit ripple-carry adder
def add4(a4, b4):
result = []
carry = 0
for i in range(4):
s, carry = full_adder(a4[i], b4[i], carry)
result.append(s)
return result, carry
# Test: 5 + 3 = 8
a = [1,0,1,0] # 5 in binary (LSB first)
b = [1,1,0,0] # 3 in binary
result, cout = add4(a, b)
print(f"5 + 3 = {int(''.join(str(b) for b in reversed(result)),2)} carry={cout}")
Implement a 1-bit multiplier (AND gate) and extend it to an 8-bit multiply-by-2 using a shift register. Then research how modern CPUs implement 64-bit integer multiplication. How many transistors does a hardware multiplier require vs a software loop that adds N times?